display-dma2d
4.0.0
display-dma2d
bsp
ui
inc
ui_drawing_dma2d_configuration.h
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/*
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* C
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*
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* Copyright 2023 MicroEJ Corp. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be found with this software.
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*/
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#ifndef UI_DRAWING_DMA2D_CONFIGURATION_H
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#define UI_DRAWING_DMA2D_CONFIGURATION_H
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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// --------------------------------------------------------------------------------
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// Includes
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// --------------------------------------------------------------------------------
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#include <stdint.h>
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// --------------------------------------------------------------------------------
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// Defines
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// --------------------------------------------------------------------------------
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/*
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* @brief Value to disable the cache management
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* @see DRAWING_DMA2D_CACHE_MANAGEMENT
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*/
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#define DRAWING_DMA2D_CACHE_MANAGEMENT_DISABLED (0U)
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/*
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* @brief Value to enable the cache management
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* @see DRAWING_DMA2D_CACHE_MANAGEMENT
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*/
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#define DRAWING_DMA2D_CACHE_MANAGEMENT_ENABLED (1U)
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#if !defined (__DCACHE_PRESENT) || (__DCACHE_PRESENT == 0U)
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/*
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* @brief This MCU does not have or does not use a cache. Cache management in
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* ui_drawing_dma2d.c is disabled.
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*/
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#define DRAWING_DMA2D_CACHE_MANAGEMENT (DRAWING_DMA2D_CACHE_MANAGEMENT_DISABLED)
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#else // !defined (__DCACHE_PRESENT) || (__DCACHE_PRESENT == 0U)
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/*
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* @brief This MCU has a cache. Cache management must be configured.
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*
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* To ensure the best SDRAM performance, the SDRAM section must be configured
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* as cacheable, write-through and shareable. As per the application notes below,
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* this is required to maintain cache coherency. If the section is not defined as shareable,
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* cache maintenance has to be performed, which adds overhead to all dma2d transfers:
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* cache clean before the transfer and cache invalidate after the transfer.
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*/
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/*
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* @brief Cache management requirements are detailed in the following documents:
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* https://www.st.com/resource/en/application_note/an4838-introduction-to-memory-protection-unit-management-on-stm32-mcus-stmicroelectronics.pdf
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* https://www.st.com/resource/en/application_note/an4839-level-1-cache-on-stm32f7-series-and-stm32h7-series-stmicroelectronics.pdf
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*
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* Cache management is not required in the following cases:
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*
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* - MCU without cache (e.g Cortex-M4)
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*
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* - Memory region containing display buffers is non-cacheable e.g.:
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* MPU_InitStruct.BaseAddress = 0xC0000000;
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* MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;
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* MPU_InitStruct.IsBufferable = MPU_ACCESS_NON_BUFFERABLE;
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* MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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* MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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* MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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* MPU_InitStruct.Number = MPU_REGION_NUMBER4;
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* HAL_MPU_ConfigRegion(&MPU_InitStruct);
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*
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* - Memory region containing display buffers is cacheable, write-through, no write allocate, shareable e.g.:
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* MPU_InitStruct.BaseAddress = 0xC0000000;
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* MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;
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* MPU_InitStruct.IsBufferable = MPU_ACCESS_NON_BUFFERABLE;
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* MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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* MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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* MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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* MPU_InitStruct.Number = MPU_REGION_NUMBER4;
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*
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* As per application note AN4839, in order to maintain cache coherency, the memory region containing
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* the display buffers and MicroUI images heap have to be configured as write-through and shareable,
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* otherwise cache maintenance operations have to be performed.
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*/
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//#define DRAWING_DMA2D_CACHE_MANAGEMENT (DRAWING_DMA2D_CACHE_MANAGEMENT_DISABLED)
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/*
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* @brief Cache management is required in the following cases:
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*
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* - MCU with cache (e.g. Cortex-M7) and the memory is configured as follows:
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*
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* - Memory region containing display buffers configured as write-back e.g.:
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* MPU_InitStruct.BaseAddress = 0xC0000000;
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* MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;
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* MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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* MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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* MPU_InitStruct.IsShareable = MPU_ACCESS_NON_SHAREABLE;
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* MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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* MPU_InitStruct.Number = MPU_REGION_NUMBER4;
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*
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* - Memory region containing display buffers configured as write-through, non-shareable e.g.:
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* MPU_InitStruct.BaseAddress = 0xC0000000;
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* MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;
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* MPU_InitStruct.IsBufferable = MPU_ACCESS_NON_BUFFERABLE;
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* MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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* MPU_InitStruct.IsShareable = MPU_ACCESS_NON_SHAREABLE;
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* MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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* MPU_InitStruct.Number = MPU_REGION_NUMBER4;
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*
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* Enabling cache management will reduce the performance of the UI, as each dma2d transfer requires
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* cache clean before the transfer and cache invalidate after the transfer to maintain cache coherency.
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*
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* Cache invalidation is performed in the DMA2D ISR, so for this reason the dma2d drawing code is placed
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* in the ITCM section to minimize the impact on performance.
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*/
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//#define DRAWING_DMA2D_CACHE_MANAGEMENT (DRAWING_DMA2D_CACHE_MANAGEMENT_ENABLED)
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#endif // !defined (__DCACHE_PRESENT) || (__DCACHE_PRESENT == 0U)
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// --------------------------------------------------------------------------------
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// EOF
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// --------------------------------------------------------------------------------
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#ifdef __cplusplus
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}
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#endif
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#endif // UI_DRAWING_DMA2D_CONFIGURATION_H
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